1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and specifically to an insulated gate semiconductor device having an insulated gate bipolar transistor and a method for manufacturing the same.
2. Background Art
In a power semiconductor element, an insulated gate bipolar transistor (hereafter abbreviated as “IGBT”) having a trench structure is widely used as a switching element. An example of IGBT structures will be described below.
An n-type base layer is formed between a first major surface and a second major surface of a semiconductor substrate, and a p-type base layer is formed on the first major surface side of the n-type base layer. In the p-type base layer, an n-type emitter layer is selectively formed. A trench is formed extending through the n-type emitter layer and the p-type base layer, and an insulating film is formed along the inner surface thereof. Through the insulating film, a gate electrode is buried in the trench. A p-type collector layer is formed on the second major surface side of the n-type base layer.
In operation of the IGBT, in other words, when a predetermined voltage is applied between the gate and the emitter, a channel is formed along the trench in the p-type base layer, the connection between the collector and the emitter is turned on, and a current flows. At this time, it is desired that the collector-emitter voltage, i.e. on-voltage is as low as possible. It is also desired that power loss when the IGBT is turned off, i.e. turn-off loss is as small as possible. In general, the reduction of the on-voltage is in a tradeoff relation with the suppression of the turn-off loss.
In Japanese Unexamined Patent Publication No. 2005-347289, the structure of IGBT wherein a carrier stored layer having a high impurity concentration than the n-type base layer is formed between the p-type base layer and the n-type base layer so as to reduce the on-voltage is disclosed.
In the above-described conventional IGBT, normally, the n-type impurity in the carrier stored layer is in normal distribution in the depth direction of the semiconductor substrate. Therefore, there was a problem wherein the thickness of the portion of the carrier stored layer having high impurity concentration was thinned, and the on-voltage could not be sufficiently reduced.